Short Write-Up of the H1Lumi DAQ Upgrade in 94-95 Winter Shutdown           
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  o Motivation:                                                                 
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    During H1 data taking 94 it was found that the Luminosity branch            
    is one of the slowest in H1CDAQ giving a visible contribution to            
    the overall H1 Dead Time.                                                   
    Front End Ready signal (FER) from the Luminosity branch                     
    was delayed sometimes significantly (up to ~100msec).                       
    This situation was originally obsereved by E. Elsen 01.06.94 and            
    was then discussed several times at the H1 Trigger Meetings.                
    One of the reasons for such a behaviour is related with many                
    different tasks performed by the lumi system, and therefore a               
    variety of applications running in a concurrent mode at online Lumi         
    processors.                                                                 
    There was also a hard limit observed related to the readout time            
    of the lumi system in the existing configuration.                           
                                                                                
    The following characteristics of the Lumi branch have been measured:        
    a) a large FER delay (with the tail up to 100msec)                          
    b) an average delay before FER = 1.632 msec with <rms> = 0.071 msec         
    c) H1 Lumi Dead Line (max L1 rate) = ~102 Hz.                               
    A little improvement has been achieved in July'94 by some s/w               
    optimization:                                                               
    - large tail of FER-delays was essentialy removed (or reduced) and          
    - H1 Lumi Dead Line (max L1 rate) became ~112 Hz.                           
                                                                                
    As a more radical solution of the problem it was proposed to iclude         
    an additional processor into the Lumi system readout.                       
                                                                                
                                                                                
  o H1Lumi DAQ improvement and upgrade:                                         
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    A switch to the double processor configuration has been successfully        
    performed by Igor Sheviakov. Some first test results showed                 
    a clear improvement already 2 weeks after data taking 94 period:            
    a) an average delay before FER was reduced to 0.8 msec and                  
    b) H1 Lumi Dead Line increased to ~150 Hz.                                  
                                                                                
    Final characteristics of the new double processor Lumi branch,              
    after including new e-tagger (ET44) into the system and further             
    software optimization, was measured to be:                                  
    a) an average delay before FER = ~1 msec,                                   
    b) H1Lumi Dead Line (max L1 event rate) = ~200 Hz.                          


  o Hardware and Equipment of the Lumi System (present status)
    ----------------------------------------------------------

 1) 5 detectors (ET, PD, VC, ET44 and small monitoring veto counter)
    with 77 channels in total and all necessary infrastructure and
    electronics both in the tunnel and in the trailer (room 101).

 2) Trigger hardware serving 3 different branches:
    - "photoproduction"(included in a standard H1 CT/CDAQ scheme)
    - "luminosity"     (stand alone, giving dead time free measurements)
    - "monitoring"     (for internal trigger  parameters monitoring)
    and consisting of both standard and original electronics.
    Electronics used in the system are of VME or CAMAC standards.

 3) 5 GPTP cards used for Lumi system itself (3) and Veto Wall (2).

 4) 11 FADCs with 16 inputs each (158 used for Lumi and 12 - for
    Neutron Counter) and with 2.56 mksec pipeline.

 5) Various processors and memory units:
    - 3 FIC 8230/31 with 68020/30 microprocessors on board (with
      coprocessors 68881) and with 512 kb of the Dual Ported Memory 
      on each board;
    - VIC-processor used to iclude Lumi system into branch 10 of H1CDAQ;
    - UNIX processor SPARC CPU-3CE/16
    - Two DPM8242 units with 2 Mb memory each;
    - Three MacII computers (2 in H1 CR and 1 in HERA CR) with the
      following configuration:
        a) H1Lumi  -  8 Mb memory + 80 Mb Hard Disk + Ethernet-card +
                        MICRON + additional large screen (VideoCard)
        b) H1Lumi2 - 20 Mb memory + 120 Mb Hard Disk + Ethernet-card +
                        MICRON + additional large screen (VideoCard) +
                        additional b/w screen (VideoCardBW) + 1 Gb 
                        additional hard disk (used for the long term
                        history of lumi and other beam related data)
        c) HKR_H1Lumi - property of HERA machine group
    - MacII-VME, MacII-CAMAC and CAMAC-VME interfaces